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secondary side average current mode controller uc1826 uc2826 uc3826 features ? practical secondary side control of isolated power supplies ? 1mhz operation ? tailored loop bandwidth provides excellent noise immunity ? voltage feedforward provides superior transient response ? accurate programmable maximum duty cycle ? multiple chips can be synchronized to fastest oscillator ? wide gain bandwidth product (70mhz, acl>10) current error amplifier ? up to ten devices can easily share a common load description the uc1826 family of average current mode controllers accurately accomplishes secondary side average current mode control. the sec- ondary side output voltage is regulated by sensing the output voltage and differentially sensing the ac switching current. the sensed output voltage drives a voltage error amplifier. the ac switching current, mon- itored by a current sense resistor, drives a high bandwidth, low offset current error amplifier. the output of the voltage error amplifier can be used to drive the current amplifier which filters the measured inductor current. fast transient response is accomplished by utilizing voltage feedforward in generating the pwm ramp. the uc1826 features load share, oscillator synchronization, undervolt- age lockout, and programmable output control. multiple chip operation can be achieved by connecting up to ten uc1826 chips in parallel. the share bus and clksyn bus provide load sharing and synchroniza- tion to the fastest oscillator respectively. with its tailored bandwidth, the uc1826 provides excellent noise immunity and is an ideal controller to achieve high power, secondary side average current mode control. 7/95 block diagram udg-95013 pin numbers refer to 24-pin packages.
absolute maximum ratings supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20v output current source or sink . . . . . . . . . . . . . . . . . . . . . .0.3a analog input voltages . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to 7v ilim, kill, seq, enbl, run, pwrsen, pwrok . . . . - 0.3v to 7v clksyn current source . . . . . . . . . . . . . . . . . . . . . . . . .20ma run current sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma seq current sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma rdead current sink . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma ramp current sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ma share bus voltage (voltage with respect to gnd) . . .0v to 6.2v adj voltage (voltage with respect to gnd) . . . . . .0.9v to 6.3v vee (voltage with respect to gnd) . . . . . . . . . . . . . . . . . . - 1.5v parameter test conditions min typ max units current error amplifier ib 0.5 3 m a vio t a = +25c 0.75 3 mv over temperature 5 mv avo 60 90 db gbw (note 2) acl = 10, r in = 1k, cc = 15pf, f = 200khz (note 1) 45 70 mhz vol i o = 1ma, voltage above vee 0.5 v voh i o = 0ma 3.8 v i o = - 1ma 3.5 v voltage error amplifier ib 0.5 3 m a vio 5mv avo 60 90 db 2 uc1826 uc2826 uc3826 storage temperature . . . . . . . . . . . . . . . . . . . . - 65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . - 65c to +150c lead temperature (soldering, 10 sec.) . . . . . . . . . . . . .+300c all voltages with respect to vee except where noted; all currents are positive into, negative out of the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. recommended operating conditions input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8v to 20v sink/source output current . . . . . . . . . . . . . . . . . . . . . .250ma timing resistor r t . . . . . . . . . . . . . . . . . . . . . . . . . .1k to 200k timing capacitor c t . . . . . . . . . . . . . . . . . . . . . . . .75pf to 2nf connection diagrams dil-24, soic-24,tssop-24 (top view) j or n, dw, pw packages plcc-28 (top view) q package electrical characteristics unless otherwise stated these specifications apply for t a = - 55 cto + 125 c for uc1826; - 40 c to + 85 c for uc2826; and 0 c to + 70 c for uc3826; vcc = 12v, vee = gnd, output no load, c t = 345pf, r t = 4k w , rdead = 1000 w , c ramp = 345pf, r ramp = 35.2k w, r clksyn = 1k, t a = t j .
3 parameter test condition min typ max units voltage error amplifier (cont.) gbw (note 2) f = 200khz 7 mhz vol i o = 175ma, volts above vee 0.6 v voh ilim = 3v 2.85 3 3.15 v voh-ilim tested ilim = 0.5v, 1.0v, 2.0v - 100 100 mv 2x amplifier and share amplifier v offset (b; y = mx + b) 20 mv gain (m; y = mx + b) slope with av out = 1v and 2v 1.98 2.02 v gbw (note 2) 100 khz r share vcc = 0, v share /i share 200 k w total offset negative supply is vee, gnd open,vao = gnd - 75 0 75 mv vol vao = voltage amp vol, volts above vee 0.2 0.45 0.6 v voh i o = 0ma, ilim = 3v, vao = voltage amp voh 5.7 6 6.3 v i o = - 1ma, ilim = 3v, vao = voltage amp voh 5.7 6 6.3 v adjust amplifier vio 40 60 80 mv gm i o = - 2 m a to 2 m a, c adj = 0.1 m f - 0. 1 - 0.3 ms vol i out = 0 0.9 1 1.1 v i out = 2 m a 0.85 1 1.15 v voh i out = 0, v share = 6.5v 5.7 6 6.3 v i out =- 2 m a, v share = 6.5v 5.7 6 6.3 v oscillator frequency 450 500 550 khz max duty cycle 72 76 80 % osc ramp amplitude 2 2.2 2.4 v ramp saturation i o = 10ma, osc = 0v 0.44 0.8 v clock driver/sync (clksyn) vol 0.02 0.2 v voh 3.6 v r clksyn = 200 w 3.5 v i source 25 ma r clksyn vcc = 0, v clksyn /i clksyn 10 k v th 1.5 v vref comparator turn-on threshold 4.65 v hysteresis 0.4 v vcc comparator turn-on threshold 7.9 8.4 8.9 v hysteresis 0.4 v pwr sense comparator voltage threshold 1.25 v vol i o = 1ma 0.3 0.4 v voh i o =- 100 m a4v kill comparator voltage threshold 3v uc1826 uc2826 uc3826 electrical characteristics (cont.) unless otherwise stated these specifications apply for t a = - 55 cto + 125 c for uc1826; - 40 c to + 85 c for uc2826; and 0 c to + 70 c for uc3826; vcc = 12v, vee = gnd, output no load, c t = 345pf, r t = 4k w , rdead = 1000 w , c ramp = 345pf, r ramp = 35.2k w, r clksyn = 1k, t a = t j .
parameter test condition min typ max units sequence comparator voltage threshold 2.5 v seq sat i o = 10ma 0.25 v enable comparator voltage threshold 2.5 v run sat i o = 10ma 0.2 v reference vref t a = 25 c 4.95 5 5.05 v vcc = 15v 4.9 5.1 v line regulation 10 < vcc < 20 3 15 mv load regulation 0 < i o < 10ma 3 15 mv short circuit i vref = 0v 30 60 90 ma output stage rise time c l = 100pf 10 20 ns fall time c l = 100pf 10 20 ns voh vcc > 11v, i o =- 10ma 8.0 8.4 8.8 v i o = - 200ma 7.8 v vol i o = 200ma 3.0 v i o = 10ma 0.5 v virtual ground v gnd - vee vee is externally supplied, gnd is floating 0.2 0.75 v and used as signal gnd. icc icc (run) 21 30 ma 4 uc1826 uc2826 uc3826 note 1: guaranteed by design. not 100% tested in production. note 2: unless otherwise specified all voltages are with respect to gnd. currents are positive into, negative out of the specified terminal. electrical characteristics (cont.) unless otherwise stated these specifications apply for t a = - 55 cto + 125 c for uc1826; - 40 c to + 85 c for uc2826; and 0 c to + 70 c for uc3826; vcc = 12v, vee = gnd, output no load, c t = 345pf, r t = 4k w , rdead = 1000 w , c ramp = 345pf, r ramp = 35.2k w, r clksyn = 1k, t a = t j . pin descriptions adj: the output of the transconductance (gm = - 0.1ms) amplifier adjusts the control voltage to maintain equal cur- rent sharing. the chip sensing the highest output current will have its output clamped to 1v. a resistor divider between vref and adj drives the control voltage (va+) for the voltage amplifier. each slave units adj voltage increases (to a maximum of 6v) its control voltage (va+) until its load current is equal to the master. the 60mv input offset on the gm amplifier guarantees that the unit sensing the highest load current is chosen as the master. the 60mv offset is guaranteed by design to be greater than the inherent offset of the gm amplifier and the buffer amplifier. while the 60mv offset represents an error in current sharing, the gain of the current and 2x amplifiers reduces it to only 30mv. the total current sense gain is the current amplifier gain. this pin needs a 0.1 m f capaci- tor to compensate the amplifier. ca-, ca+: the inverting and non-inverting inputs to the current error amplifier. this amplifier needs a capacitor between ca- and cao to set its dominant pole. cao: the output of the current error amplifier which is internally clamped to 4v. it is internally connected to the inverting input of the pwm comparator. clksyn: the clock and synchronization pin for the oscillator. this is a bidirectional pin that can be used to synchronize several chips to the fastest oscillator. its input synchronization threshold is 1.4v. the clksyn voltage is 3.6v when the oscillator capacitor c t is being discharged, otherwise it is 0v.
enbl: the active low input with a 2.5v threshold enables the output to switch. seq and run are driven low when enbl is above its 2.5v threshold. gnd: the signal ground used for the voltage sense amplifier, current error amplifier, current error amplifier, voltage reference, 2x amplifier, and share amplifier. the output sink transistor is wired directly to this pin. kill: the active low input with a 3.0v threshold stops the output from switching. once this function is activated run must be cycled low by driving kill above 3.0v and either resetting the power to the chip (vcc) or resetting the enbl signal. ilim: a voltage on this pin programs the voltage error amplifiers voh clamp. the voltage error amplifier output represents the average output current. the voh clamp con- sequently limits the output current. if ilim is tied to vref, it defaults to 3.0v. a voltage less than 3.0v connected to ilim clamps the voltage error amplifier at this voltage and consequently limits the maximum output current. osc: the oscillator ramp (not to be confused with pwm ramp) pin has a capacitor c t to ground and two resistors in series r t and r dead to vref. the total resistance of r t and r dead divided by vref - v osc sets exponential charge current. the oscillator charges from 1.2v to 3.4v until the output transitions low. at this time an open col- lector transistor is turned on and discharges the c t capacitor through rdead. the charge time is approximately t charge = 2(r t + r dead ) c t when the r dead resistor is used. the dead time is approximately t discharge = 2 r dead c t . 1 t charge + t discharge t charge t charge + t discharge the c t capacitance should be increased by approxi- mately 40pf to account for parasitic capacitance. out: the output of the pwm driver. it has an upper clamp of 8.5v. the peak current sink and source are 250ma. all uvlo, seq, enbl, and kill logic either enable or disable the output driver. pwrsen: this pin is the input to the pwrok comparator. pwrok: the output pin from the pwrok comparator. it has a 300 m a current source output when driven high. ramp: an open collector that can sink 20ma to dis- charge the oscillator capacitor. an rc is tied between vcc and gnd to accomplish feedforward. the pwm output drives this pin. when the output is high, the tran- sistor is off enabling the charging of the ramp capacitor. when the output transitions low, the transistor is turned on discharging the ramp capacitor. the voltage at ramp rises from 0.2v to near 4v at maximum duty cycle. although this is an exponential ramp at high vcc voltage the ramp appears linear. rdead: the pin that programs the maximum duty cycle by connecting a resistor between it and osc. the maxi- mum duty cycle is decreased by increasing this resistor value which increases the discharge time. the dead time, the time when the output is low, is 2 r dead c t . the c t capacitance should be increased by approxi- mately 40pf to account for parasitic capacitance. run: this is an open collector logic output that signifies when the chip is operational. run is pulled high to vref through an external resistor when vcc is greater than 8.4v, vref is greater than 4.65v, seq is greater than 2.5v, and kill lower than 3.0v. run connected to the va+ pin and to a capacitor to ground adds an rc rise time on the va+ pin initiating a soft start. seq: the sequence pin allows the sequencing of startup for multiple units. a resistor between vref and seq and a capacitor between seq and gnd create a unique rc rise time for each unit which sequences the output startup. share: the nearly dc voltage representing the average output current. this pin is wired directly to all share pins and is the load share bus. va-, va+: the inverting and non-inverting inputs to the voltage error amplifier. vao: the output of the voltage error amplifier. its voh is clamped with the ilim pin. vcc: the input voltage to the chip. the chip is opera- tional between 8.4v and 20v. vee: the negative supply voltage to the chip which pow- ers the lower voltage rail for all amplifiers. the chip is operational if vee is connected to gnd or if gnd is floating. when voltage is applied externally to vee, gnd becomes a virtual ground because of an internal diode between vee and gnd. the gnd current flows through the forward biased diode and out vee. gnd is always the signal ground from which the voltage reference and all amplifier inputs are referenced. vref: the reference voltage equal to 5.0v. 5 uc1826 uc2826 uc3826 (1) frequency ? (2) maximum duty cycle ? pin descriptions (cont.)
6 circuit description: pwm oscillator: the chip has two pins that set rc time constants. the resistor and capacitor tied to ramp cre- ate the ramp used as the input to the pwm comparator. when the output pin out is high, ramp charges until it passes the pwm comparator threshold. the output is then driven low and ramp is discharged. the resistors and capacitor on the osc pin are used to set the pwm operating frequency and its maximum duty cycle. the oscillator block diagram with external wiring is shown in figure 1. osc has a capacitor (c t ) to ground and two resistors in series (r t and r dead ) to vref. the total resistance of r t and r dead divided by vref - v osc sets the exponential charge current. the oscillator charges from 1.2v to a 3.4v threshold with an rc time delay of 2 c t (r dead + r t ). after exceeding this threshold, the rs flip-flop is set driving clksyn high and rdead low which discharges c t . at this time and open collector transistor is turned on and discharges c t capacitor through rdead with a rc time delay of 2 c t r dead . the oscillator and ramp waveforms are shown in figure 2. equations to attain frequency and maximum duty cycle are listed under the osc pin description. as shown in figure 3, several oscillators are synchro- nized to the highest free running frequency by connect- ing 100pf capacitors in series with each clksyn pin and connecting the other side of the capacitors together forming the clksyn bus. the clksyn bus is then pulled down to ground with a resistance of approximately 10k. referring to figure 1, the synchronization threshold is 1.4v. the oscillator blanks any synchronization pulse that occurs when osc is below 2.5v. this allows units, once they discharge below 2.5v, to continue through the current discharge and subsequent charge cycles whether or not other units on the clksyn bus are still synchronizing. this requires the frequency of all free run- ning oscillators to be within 40% of each other to guaran- tee synchronization. grounds, voltage sensing and current sensing: the voltage is sensed directly at the load. proper load shar- ing requires the same sensed voltage for each power supply connected in parallel. referring to figure 4, the uc1826 uc2826 uc3826 osc out clksyn ramp cao 3.0- 1.0 figure 2. oscillator and pwm output waveform figure 1. oscillator block with external connections udg-95014-1
7 positive sense voltage (vsp) connects to the voltage error amplifier inverting terminal (va-), the return lead for the on-chip reference is used as the negative sense (vsm). the current is sensed across the shunt resistor, r s . the voltage across the shunt resistor is level shifted up so that the maximum voltage across rs corresponds to the voltage error amplifier voh. figure 4 shows one recommended voltage and current sensing scheme when vee is connected to gnd. the signal ground is the negative sense point for the output voltage and the positive sense point for the output cur- rent. vee is the negative supply for the current sense amplifier. when it is separated from gnd, it extends the current sense amplifiers common mode input voltage range to include vee which is approximately - 0.7v below ground. the resistor r adj is used for load sharing. the unit which is the master will force v adj to 1.0v. therefore, the regulated voltage being sensed is actually r adj r1 + r adj vsm = 0v, v adj = 1v (master), vref = 5v r adj r1 + r adj the voltage at adj on the slave chips will increase forc- ing their load currents to increase to match the master. the ac frequency response of the voltage error amplifier is shown in figure 5. startup and shutdown: isolated power up can be accomplished using the ucc1889. application note u-149 is available for additional information. the uc1826 offers several features that enhance startup and shutdown. soft start is accomplished by connecting run to va+ and a capacitor to ground. the resulting rc rise time on the va+ pin initiates a soft start. it can also be accomplished by connecting run to ilim. when run is low it will command zero load current, guaranteeing a soft start. the undervoltage lockout (uvlo) is a logical and of enbl < 2.5v, seq > 2.5v, vcc > 8.4v and figure 3. oscillator synchronization connection diagram figure 4. voltage and current sense vee tied to gnd vsp - vsm = (vref - v adj ) () + v adj vsp = 4 () + 1v uc1826 uc2826 uc3826 circuit block description (cont.) ? ? m figure 5. ac frequency response of the voltage error amplifier udg-95015 udg-95016
8 uc1826 uc2826 uc3826 vref > 4.65v. the block diagram shows that the thresh- olds are set by comparators. by placing an rc divider on the seq pin, the enabling of multiple chips can be sequenced with different rc time constants. similarly, different rc time constants on the enbl pins can sequence shutdown. the uvlo keeps the output from switching; however the internal reference starts up with vcc less than 8.4v. the kill input shuts down the switching of the chip. this can be used in conjunction with an overvoltage comparator for overvoltage protec- tion. in order to restart the chip after kill has been initi- ated, the chip must be powered down and then back up. a pulse on the enbl pin also accomplishes this without actually removing voltage to the vcc pin. load sharing: load sharing is accomplished similarly to the uc1907 except it has the added constraint of using the sensed current for average current mode control. the sensed current for the uc1826 has an ac component that is amplified and then averaged. the voltage error amplifier represents this average current. the voltage error amplifier output is the current command signal and its voltage represents the average output load current. the ilim pin programs the upper clamp voltage of this amplifier and consequently the maximum load current. a gain of 2 amplifier connected between the voltage error amplifier output and the share amplifier input increases the current share resolution and noise margin. the aver- age current is used as an input to a source only load share buffer amplifier. the output of this amplifier is the current share bus. the ic with the highest sensed cur- rent will have the highest voltage on the current share bus and consequently act as the master. the 60mv input offset guarantees that the unit sensing the highest load current is chosen as the master. the adjust amplifier is used by the remaining (slave) ics to adjust their respective references high in order to bal- ance each ics load current. the masters adj pin will be at its 1.0v clamp and connected back to the non-invert- ing voltage error amplifier input through a high value resistor. this requires the user to initially calculate the control voltage with the adj pin at 1.0v. vref can be adjusted 150mv to 300mv which compen- sates for 5% unit to unit reference mismatch and external resistor mismatch. r adj will typically be 10 to 30 times larger than r1. this also attenuates the overall variation of the adj clamp of 1v 100mv by a factor of 10 to 30, con- tributing only a 3mv to 10mv additional delta to vref. refer to the uc3907 application note u-130 for further information on parallel power supply load sharing. current control loop: the current error amplifier (cea) needs its loop compensated externally. the zero crossing can be calculated with equation 3. 1 2 p r inv c comp r inv is the input resistance at the inverting terminal ca- c comp is the capacitance between ca- and cao. although it is only unity gain stable for a bw of 7mhz, the amplifier is typically configured with a differential gain of at least 10, allowing the amplifier to operate with suffi- cient phase margin at a gbw of 70mhz. a closed loop gain of 10 attenuates the output by 20.8db 1 11 to the inverting terminal assuring stability. the amplifiers gain fed back into the inverting terminal is less than unity at 7mhz, where the phase margin begins to roll off. see figure 6 for a typical bode plot. the current error amplifier bandwidth is rolled off and controlled by the voltage error amplifier output. the maxi- mum load current is limited to approximately the maxi- mum voltage across the shunt resistor (maximum of 200mv) divided by r s : v rs r s ilim sets the maximum current limit by setting the voh clamp on the voltage error amplifier. if ilim is not set to limit the voh to be equal to the maximum voltage across r s , vao must be attenuated to match the maximum volt- circuit block description (cont.) (3) frequency (0db) = 20.8 = 20log b ? m - figure 6. current error amplifier bode plot (4) i maxload =
age v r s across the shunt resistor. by attenuating the maximum voltage at vao to be equal to v r s , the current control loop keeps the load from exceeding its current limit. if the ilim pin is connected to vref, the voh is set at 3.0v. the maximum current limit clamp can be reduced by reducing the voltage on ilim to less than 3.0v as described in the ilim pin description. design example: figure 7 is an open loop test that lets the user test the circuit blocks discussed without having to build an entire control loop. the pulse width can be varied by either the v adj or the vi sense inputs. figure 8 shows an isolated power supply using the uc1826 sec- ondary side average current mode controller. uc1826 uc2826 uc3826 circuit block description (cont.) figure 7. open loop circuit 9 udg-95017-1
10 unitrode integrated circuits 7 continental blvd. ? merrimack, nh 03054 tel. 603-424-2410 ? fax 603-424-3460 figure 8. uc1826 application diagram uc1826 uc2826 uc3826
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